/*
 * Copyright : (C) 2023 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK3588_PARAMTERERS_H
#define RK3588_PARAMTERERS_H

#ifdef __cplusplus
extern "C"
{
#endif

/* SGRF */
#define PMU0_SGRF_BASE_ADDR         0xFD580000U
#define PMU1_SGRF_BASE_ADDR         0xFD582000U
#define BUS_SGRF_BASE_ADDR          0xFD586000U
#define DSU_SGRF_BASE_ADDR          0xFD587000U

/* GRF */
#define GRF_EMMC_DETECT_IRQ_NUM 308
#define GRF_USB2HOST0_PHY_IRQ_NUM 423
#define GRF_USB2HOST1_PHY_IRQ_NUM 424
#define GRF_OTG0_PHY_IRQ_NUM 425
#define GRF_OTG1_PHY_IRQ_NUM 426

#define PMU0_GRF_BASE_ADDR          0xFD588000U
#define PMU1_GRF_BASE_ADDR          0xFD58A000U
#define SYS_GRF_BASE_ADDR           0xFD58C000U
#define BIGCORE0_GRF_BASE_ADDR      0xFD590000U
#define BIGCORE1_GRF_BASE_ADDR      0xFD592000U
#define LITCORE_GRF_BASE_ADDR       0xFD594000U
#define DSU_GRF_BASE_ADDR           0xFD598000U
#define DDR01_GRF_BASE_ADDR         0xFD59C000U
#define DDR23_GRF_BASE_ADDR         0xFD59D000U
#define CENTER_GRF_BASE_ADDR        0xFD59E000U
#define GPU_GRF_BASE_ADDR           0xFD5A0000U
#define NPU_GRF_BASE_ADDR           0xFD5A2000U
#define VOP_GRF_BASE_ADDR           0xFD5A4000U
#define VO0_GRF_BASE_ADDR           0xFD5A6000U
#define VO1_GRF_BASE_ADDR           0xFD5A8000U
#define USB_GRF_BASE_ADDR           0xFD5AC000U
#define PHP_GRF_BASE_ADDR           0xFD5B0000U
#define CSIDPHY0_GRF_BASE_ADDR      0xFD5B4000U
#define CSIDPHY1_GRF_BASE_ADDR      0xFD5B5000U
#define PCIE3PHY_GRF_BASE_ADDR      0xFD5B8000U
#define PIPE_PHY0_GRF_BASE_ADDR     0xFD5BC000U
#define PIPE_PHY1_GRF_BASE_ADDR     0xFD5C0000U
#define PIPE_PHY2_GRF_BASE_ADDR     0xFD5C4000U
#define USBDPPHY0_GRF_BASE_ADDR     0xFD5C8000U
#define USBDPPHY1_GRF_BASE_ADDR     0xFD5CC000U
#define USB2PHY0_GRF_BASE_ADDR      0xFD5D0000U
#define USB2PHY1_GRF_BASE_ADDR      0xFD5D4000U
#define USB2PHY2_GRF_BASE_ADDR      0xFD5D8000U
#define USB2PHY3_GRF_BASE_ADDR      0xFD5DC000U
#define HDPTXPHY0_GRF_BASE_ADDR     0xFD5E0000U
#define HDPTXPHY1_GRF_BASE_ADDR     0xFD5E4000U
#define MIPICDPHY0_GRF_BASE_ADDR    0xFD5E8000U
#define MIPICDPHY1_GRF_BASE_ADDR    0xFD5EC000U
#define PMU1_IOC_BASE_ADDR          0xFD5F0000U
#define PMU2_IOC_BASE_ADDR          0xFD5F4000U
#define BUS_IOC_BASE_ADDR           0xFD5F8000U
#define VCCIO1_4_IOC_BASE_ADDR      0xFD5F9000U
#define VCCIO3_5_IOC_BASE_ADDR      0xFD5FA000U
#define VCCIO2_IOC_BASE_ADDR        0xFD5FB000U
#define VCCIO6_IOC_BASE_ADDR        0xFD5FC000U
#define EMMC_IOC_BASE_ADDR          0xFD5FD000U

/* GPIO */
#if !defined(__ASSEMBLER__)
enum {
    GPIO0_ID = 0,
    GPIO1_ID,
    GPIO2_ID,
    GPIO3_ID,
    GPIO4_ID,
    GPIO_NUM
};
#endif

#define GPIO0_IRQ_NUM 309
#define GPIO1_IRQ_NUM 310
#define GPIO2_IRQ_NUM 311
#define GPIO3_IRQ_NUM 312
#define GPIO4_IRQ_NUM 313
#define GPIO0_EXP_IRQ_NUM 314
#define GPIO1_EXP_IRQ_NUM 315
#define GPIO2_EXP_IRQ_NUM 316
#define GPIO3_EXP_IRQ_NUM 317
#define GPIO4_EXP_IRQ_NUM 318

#define GPIO0_BASE_ADDR 0xFD8A0000U
#define GPIO1_BASE_ADDR 0xFEC20000U
#define GPIO2_BASE_ADDR 0xFEC30000U
#define GPIO3_BASE_ADDR 0xFEC40000U
#define GPIO4_BASE_ADDR 0xFEC50000U
#define GPIO_REG_LENGTH 0x10000U /* 64KB */

/* PWM */
#if !defined(__ASSEMBLER__)
enum {
    PWM0_ID = 0,
    PWM1_ID,
    PWM2_ID,
    PWM3_ID,
    PWM_NUM
};
#endif

#define PWM0_IRQ_NUM 376
#define PWM1_IRQ_NUM 378
#define PWM2_IRQ_NUM 380
#define PWM3_IRQ_NUM 382
#define PWM0_PWR_IRQ_NUM 377
#define PWM1_PWR_IRQ_NUM 378
#define PWM2_PWR_IRQ_NUM 381
#define PWM3_PWR_IRQ_NUM 383

#define PWM0_BASE_ADDR 0xFD8B0000U
#define PWM1_BASE_ADDR 0xFEBD0000U
#define PWM2_BASE_ADDR 0xFEBE0000U
#define PWM3_BASE_ADDR 0xFEBF0000U
#define PWM_REG_LENGTH 0x10000U /* 64KB */

/* DMAC */
#if !defined(__ASSEMBLER__)
enum {
    DMAC0_ID = 0,
    DMAC1_ID,
    DMAC2_ID,
    DMAC_NUM
};
#endif

#define DMAC0_IRQ_NUM 118
#define DMAC0_ABORT_IRQ_NUM 119
#define DMAC1_IRQ_NUM 120
#define DMAC1_ABORT_IRQ_NUM 121
#define DMAC2_IRQ_NUM 122
#define DMAC3_ABORT_IRQ_NUM 123

#define DMAC0_NS_BASE_ADDR 0xFEA10000U
#define DMAC1_NS_BASE_ADDR 0xFEA30000U
#define DMAC2_NS_BASE_ADDR 0xFED10000U

#define DMAC0_S_BASE_ADDR  0xFEA00000U
#define DMAC1_S_BASE_ADDR  0xFEA20000U
#define DMAC2_S_BASE_ADDR  0xFED00000U

#define DMAC_REG_LENGTH    0x10000U /* 64KB */

/* I2C */
#if !defined(__ASSEMBLER__)
enum {
    I2C0_ID = 0,
    I2C1_ID,
    I2C2_ID,
    I2C3_ID,
    I2C4_ID,
    I2C5_ID,
    I2C6_ID,
    I2C7_ID,
    I2C8_ID,
    I2C_NUM
};
#endif

#define I2C0_IRQ_NUM 349
#define I2C1_IRQ_NUM 350
#define I2C2_IRQ_NUM 351
#define I2C3_IRQ_NUM 352
#define I2C4_IRQ_NUM 353
#define I2C5_IRQ_NUM 354
#define I2C6_IRQ_NUM 355
#define I2C7_IRQ_NUM 356
#define I2C8_IRQ_NUM 357

#define I2C0_BASE_ADDR 0xFD880000U
#define I2C1_BASE_ADDR 0xFEA90000U
#define I2C2_BASE_ADDR 0xFEAA0000U
#define I2C3_BASE_ADDR 0xFEAB0000U
#define I2C4_BASE_ADDR 0xFEAC0000U
#define I2C5_BASE_ADDR 0xFEAD0000U
#define I2C6_BASE_ADDR 0xFEC80000U
#define I2C7_BASE_ADDR 0xFEC90000U
#define I2C8_BASE_ADDR 0xFECA0000U
#define I2C_REG_LENGTH 0x10000U /* 64KB */

/* SPI */
#if !defined(__ASSEMBLER__)
enum {
    SPI0_ID = 0,
    SPI1_ID,
    SPI2_ID,
    SPI3_ID,
    SPI4_ID,
    SPI_NUM
};
#endif

#define SPI0_IRQ_NUM 358
#define SPI1_IRQ_NUM 359
#define SPI2_IRQ_NUM 360
#define SPI3_IRQ_NUM 361
#define SPI4_IRQ_NUM 362

#define SPI0_BASE_ADDR 0xFEB00000U
#define SPI1_BASE_ADDR 0xFEB10000U
#define SPI2_BASE_ADDR 0xFEB20000U
#define SPI3_BASE_ADDR 0xFEB30000U
#define SPI4_BASE_ADDR 0xFECB0000U
#define SPI_REG_LENGTH 0x10000U /* 64KB */

/* UART */
#if !defined(__ASSEMBLER__)
enum {
    UART0_ID = 0,
    UART1_ID,
    UART2_ID,
    UART3_ID,
    UART4_ID,
    UART5_ID,
    UART6_ID,
    UART7_ID,
    UART8_ID,
    UART9_ID,
    UART_NUM
};
#endif

#define UART0_IRQ_NUM 363
#define UART1_IRQ_NUM 364
#define UART2_IRQ_NUM 365
#define UART3_IRQ_NUM 366
#define UART4_IRQ_NUM 367
#define UART5_IRQ_NUM 368
#define UART6_IRQ_NUM 369
#define UART7_IRQ_NUM 370
#define UART8_IRQ_NUM 371
#define UART9_IRQ_NUM 372

#define UART0_BASE_ADDR 0xFD890000U
#define UART1_BASE_ADDR 0xFEB40000U
#define UART2_BASE_ADDR 0xFEB50000U
#define UART3_BASE_ADDR 0xFEB60000U
#define UART4_BASE_ADDR 0xFEB70000U
#define UART5_BASE_ADDR 0xFEB80000U
#define UART6_BASE_ADDR 0xFEB90000U
#define UART7_BASE_ADDR 0xFEBA0000U
#define UART8_BASE_ADDR 0xFEBB0000U
#define UART9_BASE_ADDR 0xFEBC0000U
#define UART_REG_LENGTH 0x10000U /* 64KB */

/* GMAC */
#if !defined(__ASSEMBLER__)
enum {
    GMAC0_ID = 0,
    GMAC1_ID = 0,
    GMAC_NUM
};
#endif

#define GMAC0_DMA_IRQ_NUM 255
#define GMAC0_LPI_IRQ_NUM 257
#define GMAC0_PMT_IRQ_NUM 258
#define GMAC0_SBD_IRQ_NUM 259
#define GMAC0_SBD_PERCH_RX0_IRQ_NUM 260
#define GMAC0_SBD_PERCH_RX1_IRQ_NUM 261
#define GMAC0_SBD_PERCH_TX0_IRQ_NUM 262
#define GMAC0_SBD_PERCH_TX1_IRQ_NUM 263

#define GMAC1_DMA_IRQ_NUM 256
#define GMAC1_LPI_IRQ_NUM 264
#define GMAC1_PMT_IRQ_NUM 265
#define GMAC1_SBD_IRQ_NUM 265
#define GMAC1_SBD_PERCH_RX0_IRQ_NUM 267
#define GMAC1_SBD_PERCH_RX1_IRQ_NUM 268
#define GMAC1_SBD_PERCH_TX0_IRQ_NUM 269
#define GMAC1_SBD_PERCH_TX1_IRQ_NUM 270

#define GMAC0_BASE_ADDR 0xFE1B0000U
#define GMAC1_BASE_ADDR 0xFE1C0000U
#define GMAC_REG_LENGTH 0x10000U /* 64KB */

/* CAN */
#if !defined(__ASSEMBLER__)
enum {
    CAN0_ID = 0,
    CAN1_ID = 0,
    CAN2_ID = 0,
    CAN_NUM
};
#endif

#define CAN0_DMA_IRQ_NUM 373
#define CAN1_DMA_IRQ_NUM 374
#define CAN2_DMA_IRQ_NUM 375

#define CAN0_BASE_ADDR 0xFEA50000U
#define CAN1_BASE_ADDR 0xFEA60000U
#define CAN2_BASE_ADDR 0xFEA70000U
#define CAN_REG_LENGTH 0x10000U /* 64KB */

/* FSPI */
#if !defined(__ASSEMBLER__)
enum {
    FSPI0_ID = 0,
    FSPI_NUM
};
#endif

#define FSPI_IRQ_NUM   238

#define FSPI_BASE_ADDR  0xFE2B0000U
#define FSPI_REG_LENGTH 0x10000U /* 64KB */

/* EMMC */
#if !defined(__ASSEMBLER__)
enum {
    EMMC0_ID = 0,
    EMMC_NUM
};
#endif

#define EMMC_IRQ_NUM   237

#define EMMC_BASE_ADDR  0xFE2E0000U
#define EMMC_REG_LENGTH 0x10000U /* 64KB */

/* SDMMC */
#if !defined(__ASSEMBLER__)
enum {
    SDMMC0_ID = 0, /* SDMMC */
    SDMMC1_ID,     /* SDIO */
    SDMMC_NUM
};
#endif

#define SDMMC0_IRQ_NUM 235
#define SDMMC1_IRQ_NUM 236

#define SDMMC0_BASE_ADDR    0xFE2C0000U
#define SDMMC1_BASE_ADDR    0xFE2D0000U
#define SDMMC_BUF_BASE_ADDR 0xFE2F0000U
#define SDMMC_REG_LENGTH    0x10000U /* 64KB */

/* SATA */
#if !defined(__ASSEMBLER__)
enum {
    SATA0_ID = 0,
    SATA1_ID,
    SATA2_ID,
    SATA_NUM
};
#endif

#define SATA0_IRQ_NUM 305
#define SATA1_IRQ_NUM 306
#define SATA2_IRQ_NUM 307

#define SATA0_BASE_ADDR 0xFE210000U
#define SATA1_BASE_ADDR 0xFE220000U
#define SATA2_BASE_ADDR 0xFE230000U
#define SATA_REG_LENGTH 0x10000U /* 64KB */

/* WDT */
#if !defined(__ASSEMBLER__)
enum {
    WDT0_ID = 0,
    WDT_NUM
};
#endif

#define WDT0_NS_IRQ_NUM 347
#define WDT0_S_IRQ_NUM  348

#define WDT_NS_BASE_ADDR  0xFEAF0000U
#define WDT_NS_REG_LENGTH 0x10000U /* 64KB */

#define WDT_S_BASE_ADDR   0xFE3E0000U
#define WDT_S_REG_LENGTH  0x10000U /* 64KB */

#define WDT_BASE_ADDR     0xFE110000U
#define WDT_REG_LENGTH    0x8000U  /* 32KB */

/* TIMER */
#if !defined(__ASSEMBLER__)
enum {
    TIMER0_ID = 0,
    TIMER1_ID,
    TIMER2_ID,
    TIMER3_ID,
    TIMER4_ID,
    TIMER5_ID,
    TIMER6_ID,
    TIMER7_ID,
    TIMER8_ID,
    TIMER9_ID,
    TIMER10_ID,
    TIMER11_ID,
    TIMER_NUM
};
#endif

#define TIMER0_NS_IRQ_NUM  321
#define TIMER1_NS_IRQ_NUM  322
#define TIMER2_NS_IRQ_NUM  323
#define TIMER3_NS_IRQ_NUM  324
#define TIMER4_NS_IRQ_NUM  325
#define TIMER5_NS_IRQ_NUM  326
#define TIMER6_NS_IRQ_NUM  327
#define TIMER7_NS_IRQ_NUM  328
#define TIMER8_NS_IRQ_NUM  329
#define TIMER9_NS_IRQ_NUM  330
#define TIMER10_NS_IRQ_NUM 331
#define TIMER11_NS_IRQ_NUM 332

#define TIMER0_N_IRQ_NUM   333
#define TIMER1_N_IRQ_NUM   334
#define TIMER2_N_IRQ_NUM   335
#define TIMER3_N_IRQ_NUM   336
#define TIMER4_N_IRQ_NUM   337
#define TIMER5_N_IRQ_NUM   338
#define TIMER6_N_IRQ_NUM   339
#define TIMER7_N_IRQ_NUM   340
#define TIMER8_N_IRQ_NUM   341
#define TIMER9_N_IRQ_NUM   342
#define TIMER10_N_IRQ_NUM  343
#define TIMER11_N_IRQ_NUM  344

#define TIMER_NS_0_BASE_ADDR 0xFEAE0000U
#define TIMER_NS_1_BASE_ADDR 0xFEAE8000U
#define TIMER_NS_REG_LENGTH  0x8000U /* 32KB */

#define TIMER_S_0_BASE_ADDR  0xFE3D0000U
#define TIMER_S_1_BASE_ADDR  0xFED30000U
#define TIMER_S_REG_LENGTH   0x10000U /* 64KB */

/* HPTIMER */
#if !defined(__ASSEMBLER__)
enum {
    HPTIMER0_ID = 0,
    HPTIMER_NUM
};
#endif

#define HPTIMER_IRQ_NUM 345

#define HPTIMER_REG_LENGTH 0x4000U /* 16KB */

#define HPTIMER_BASE_ADDR  0xFD8C8000U

/* USB */
#if !defined(__ASSEMBLER__)
enum {
    USB3OTG0_ID = 0,
    USB3OTG1_ID,
    USB3OTG2_ID,
    USB2HOST0_ID,
    USB2HOST1_ID,
    USB_NUM
};
#endif

#define USB3OTG0_IRQ_NUM 252
#define USB3OTG1_IRQ_NUM 253
#define USB3OTG2_IRQ_NUM 254
#define USB2HOST0_ARB_IRQ_NUM  246
#define USB2HOST0_EHCI_IRQ_NUM 247
#define USB2HOST0_OHCI_IRQ_NUM 248
#define USB2HOST1_ARB_IRQ_NUM  249
#define USB2HOST1_EHCI_IRQ_NUM 250
#define USB2HOST1_OHCI_IRQ_NUM 251

#define USB3OTG0_BASE_ADDR   0xFC000000U
#define USB3OTG1_BASE_ADDR   0xFC400000U
#define USB3OTG2_BASE_ADDR   0xFCD00000U
#define USB2HOST0_BASE_ADDR  0xFC480000U
#define USB2HOST1_BASE_ADDR  0xFC488000U
#define USBDP_PHY0_BASE_ADDR 0xFED80000U
#define USBDP_PHY1_BASE_ADDR 0xFED90000U

/* CSI */
#if !defined(__ASSEMBLER__)
enum {
    CSI0_ID = 0,
    CSI1_ID,
    CSI2_ID,
    CSI3_ID,
    CSI4_ID,
    CSI5_ID,
    CSI_NUM
};
#endif

#define CSI_HOST_REG_LENGTH 0x10000U /* 64KB */

#define CSI_HOST0_BASE_ADDR 0xFDD10000U
#define CSI_HOST1_BASE_ADDR 0xFDD20000U
#define CSI_HOST2_BASE_ADDR 0xFDD30000U
#define CSI_HOST3_BASE_ADDR 0xFDD40000U
#define CSI_HOST4_BASE_ADDR 0xFDD50000U
#define CSI_HOST5_BASE_ADDR 0xFDD60000U

/* DSI */
#if !defined(__ASSEMBLER__)
enum {
    DSI0_ID = 0,
    DSI1_ID,
    DSI_NUM
};
#endif

#define DSI_HOST_REG_LENGTH 0x10000U /* 64KB */

#define DSI_HOST0_BASE_ADDR 0xFDE20000U
#define DSI_HOST1_BASE_ADDR 0xFDE30000U

/* DP */
#if !defined(__ASSEMBLER__)
enum {
    DP0_ID = 0,
    DP1_ID,
    DP_NUM
};
#endif

#define DP0_IRQ_NUM 193
#define DP1_IRQ_NUM 194

#define DP0_BASE_ADDR 0xFDE50000U
#define DP1_BASE_ADDR 0xFDE60000U
#define DP_REG_LENGTH 0x10000U /* 64KB */

/* eDP */
/* DP */
#if !defined(__ASSEMBLER__)
enum {
    EDP0_ID = 0,
    EDP1_ID,
    EDP_NUM
};
#endif

#define EDP0_IRQ_NUM 195
#define EDP1_IRQ_NUM 196

#define EDP0_NS_BASE_ADDR 0xFDEC0000U
#define EDP1_NS_BASE_ADDR 0xFDED0000U
#define EDP0_S_BASE_ADDR  0xFDF18000U
#define EDP1_S_BASE_ADDR  0xFDF1C000U
#define EDP_REG_LENGTH    0x10000U /* 64KB */

/* HDMI */
#if !defined(__ASSEMBLER__)
enum {
    HDMI0_ID = 0,
    HDMI_NUM
};
#endif

#define HDMI0_TX0_BASE_ADDR    0xFDE80000U
#define HDMI0_TX1_BASE_ADDR    0xFDEA0000U
#define HDMI0_RX_BASE_ADDR     0xFDEE0000U
#define HDMI0_RX_S_BASE_ADDR   0xFDF10000U
#define HDMI0_RX_PHY_BASE_ADDR 0xFEDE0000U

/* MIPI */
#if !defined(__ASSEMBLER__)
enum {
    MIPI0_ID = 0,
    MIPI_NUM
};
#endif

#define MIPI_CD_PHY0_BASE_ADDR  0xFEDA0000U
#define MIPI_CD_PHY1_BASE_ADDR  0xFEDB0000U
#define MIPI_CSI_PHY0_BASE_ADDR 0xFEDC0000U
#define MIPI_CSI_PHY1_BASE_ADDR 0xFEDC8000U

/* I2S */
#if !defined(__ASSEMBLER__)
enum {
    I2S0_ID = 0,
    I2S1_ID,
    I2S2_ID,
    I2S3_ID,
    I2S4_ID,
    I2S5_ID,
    I2S6_ID,
    I2S7_ID,
    I2S8_ID,
    I2S9_ID,
    I2S10_ID,
    I2S_NUM
};
#endif

#define I2S0_8CH_IRQ_NUM  212
#define I2S1_8CH_IRQ_NUM  213
#define I2S2_2CH_IRQ_NUM  214
#define I2S3_2CH_IRQ_NUM  215
#define I2S4_8CH_IRQ_NUM  216
#define I2S5_8CH_IRQ_NUM  217
#define I2S6_8CH_IRQ_NUM  218
#define I2S7_8CH_IRQ_NUM  219
#define I2S8_8CH_IRQ_NUM  220
#define I2S9_8CH_IRQ_NUM  221
#define I2S10_8CH_IRQ_NUM 222

#define I2S0_8CH_BASE_ADDR  0xFE470000U
#define I2S1_8CH_BASE_ADDR  0xFE480000U
#define I2S2_2CH_BASE_ADDR  0xFE490000U
#define I2S3_2CH_BASE_ADDR  0xFE4A0000U
#define I2S4_8CH_BASE_ADDR  0xFDDC0000U
#define I2S5_8CH_BASE_ADDR  0xFDDF0000U
#define I2S6_8CH_BASE_ADDR  0xFDDF4000U
#define I2S7_8CH_BASE_ADDR  0xFDDF8000U
#define I2S8_8CH_BASE_ADDR  0xFDDC8000U
#define I2S9_8CH_BASE_ADDR  0xFDDFC000U
#define I2S10_8CH_BASE_ADDR 0xFDE00000U

/* PDM */
#if !defined(__ASSEMBLER__)
enum {
    PDM0_ID = 0,
    PDM1_ID,
    PDM_NUM
};
#endif

#define PDM0_IRQ_NUM 223
#define PDM1_IRQ_NUM 224

#define PDM0_BASE_ADDR 0xFE4B0000U
#define PDM1_BASE_ADDR 0xFE4C0000U

/* SPDIF */
#if !defined(__ASSEMBLER__)
enum {
    SPDIF0_ID = 0,
    SPDIF1_ID,
    SPDIF2_ID,
    SPDIF3_ID,
    SPDIF4_ID,
    SPDIF5_ID,
    SPDIF_NUM
};
#endif

#define SPDIF0_TX_IRQ_NUM 225
#define SPDIF1_TX_IRQ_NUM 226
#define SPDIF2_TX_IRQ_NUM 227
#define SPDIF3_TX_IRQ_NUM 228
#define SPDIF4_TX_IRQ_NUM 229
#define SPDIF5_TX_IRQ_NUM 230
#define SPDIF0_RX_IRQ_NUM 231
#define SPDIF1_RX_IRQ_NUM 232
#define SPDIF2_RX_IRQ_NUM 233

#define SPDIF_TX0_BASE_ADDR 0xFE4E0000U
#define SPDIF_TX1_BASE_ADDR 0xFE4F0000U
#define SPDIF_TX2_BASE_ADDR 0xFDDB0000U
#define SPDIF_TX3_BASE_ADDR 0xFDDE0000U
#define SPDIF_TX4_BASE_ADDR 0xFDDE8000U
#define SPDIF_TX5_BASE_ADDR 0xFDDB8000U
#define SPDIF_RX0_BASE_ADDR 0xFDE08000U
#define SPDIF_RX1_BASE_ADDR 0xFDE10000U
#define SPDIF_RX2_BASE_ADDR 0xFDE18000U

/* KEYLAD */
#if !defined(__ASSEMBLER__)
enum {
    KEYLAD0_ID = 0,
    KEYLAD_NUM
};
#endif

#define KEYLAD_IRQ_NUM 239

#define KEYLADDER_S_BASE_ADDR 0xFE380000U

/* CRYPTO */
#if !defined(__ASSEMBLER__)
enum {
    CRYPTO0_ID = 0,
    CRYPTO_NUM
};
#endif

#define CRYPTO_NS_IRQ_NUM 241
#define CRYPTO_S_IRQ_NUM  240

#define CRYPTO_NS_BASE_ADDR  0xFE370000U
#define CRYPTO_S_S_BASE_ADDR 0xFE390000U
#define CRYPTO_S_K_BASE_ADDR 0xFE420000U

/* TRNG */
#if !defined(__ASSEMBLER__)
enum {
    TRNG0_ID = 0,
    TRNG_NUM
};
#endif

#define TRNG_NS_IRQ_NUM 432
#define TRNG_S_IRQ_NUM  431

#define TRNG_NS_BASE_ADDR   0xFE380000U
#define TRNG_S_BASE_ADDR    0xFE398000U

/* SPINLOCK */
#if !defined(__ASSEMBLER__)
enum {
    SPINLICK0_ID = 0,
    SPINLICK_NUM
};
#endif

#define SPINLOCK_BASE_ADDR  0xFE5A0000U

/* MAILBOX( for MCU) */
#if !defined(__ASSEMBLER__)
enum {
    MAILBOX0_ID = 0,
    MAILBOX1_ID,
    MAILBOX2_ID,
    MAILBOX_NUM
};
#endif

#define MAILBOX0_AP0_IRQ_NUM 93
#define MAILBOX0_AP1_IRQ_NUM 94
#define MAILBOX0_AP2_IRQ_NUM 95
#define MAILBOX0_AP3_IRQ_NUM 96
#define MAILBOX0_BB0_IRQ_NUM 97
#define MAILBOX0_BB1_IRQ_NUM 98
#define MAILBOX0_BB2_IRQ_NUM 99
#define MAILBOX0_BB3_IRQ_NUM 100
#define MAILBOX1_AP0_IRQ_NUM 101
#define MAILBOX1_AP1_IRQ_NUM 102
#define MAILBOX1_AP2_IRQ_NUM 103
#define MAILBOX1_AP3_IRQ_NUM 104
#define MAILBOX1_BB0_IRQ_NUM 105
#define MAILBOX1_BB1_IRQ_NUM 106
#define MAILBOX1_BB2_IRQ_NUM 107
#define MAILBOX1_BB3_IRQ_NUM 108
#define MAILBOX2_AP0_IRQ_NUM 109
#define MAILBOX2_AP1_IRQ_NUM 110
#define MAILBOX2_AP2_IRQ_NUM 111
#define MAILBOX2_AP3_IRQ_NUM 112
#define MAILBOX2_BB0_IRQ_NUM 113
#define MAILBOX2_BB1_IRQ_NUM 114
#define MAILBOX2_BB2_IRQ_NUM 115
#define MAILBOX2_BB3_IRQ_NUM 116

#define MAILBOX0_BASE_ADDR   0xFEC60000U
#define MAILBOX1_BASE_ADDR   0xFEC70000U
#define MAILBOX2_BASE_ADDR   0xFECE0000U

/* PCIE3 */
#if !defined(__ASSEMBLER__)
enum {
    PCIE3_X1_0_ID = 0,
    PCIE3_X1_1_ID,
    PCIE3_X1_2_ID,
    PCIE3_X2_ID,
    PCIE3_X4_ID,
    PCIE3_NUM
};
#endif

#define PCIE3_X1_0_ERR_IRQ_NUM    271
#define PCIE3_X1_0_LEGACY_IRQ_NUM 272
#define PCIE3_X1_0_MSG_RX_IRQ_NUM 273
#define PCIE3_X1_0_PMC_IRQ_NUM    274
#define PCIE3_X1_0_SYS_IRQ_NUM    275
#define PCIE3_X1_0_DTMI_IRQ_NUM   296
#define PCIE3_X1_1_ERR_IRQ_NUM    276
#define PCIE3_X1_1_LEGACY_IRQ_NUM 277
#define PCIE3_X1_1_MSG_RX_IRQ_NUM 278
#define PCIE3_X1_1_PMC_IRQ_NUM    279
#define PCIE3_X1_1_SYS_IRQ_NUM    280
#define PCIE3_X1_1_DTMI_IRQ_NUM   297
#define PCIE3_X1_2_ERR_IRQ_NUM    281
#define PCIE3_X1_2_LEGACY_IRQ_NUM 282
#define PCIE3_X1_2_MSG_RX_IRQ_NUM 283
#define PCIE3_X1_2_PMC_IRQ_NUM    284
#define PCIE3_X1_2_SYS_IRQ_NUM    285
#define PCIE3_X1_2_DTMI_IRQ_NUM   298
#define PCIE3_X2_ERR_IRQ_NUM      286
#define PCIE3_X2_LEGACY_IRQ_NUM   287
#define PCIE3_X2_MSG_RX_IRQ_NUM   288
#define PCIE3_X2_PMC_IRQ_NUM      289
#define PCIE3_X2_SYS_IRQ_NUM      290
#define PCIE3_X2_DTMI_IRQ_NUM     299
#define PCIE3_X4_ERR_IRQ_NUM      291
#define PCIE3_X4_LEGACY_IRQ_NUM   292
#define PCIE3_X4_MSG_RX_IRQ_NUM   293
#define PCIE3_X4_PMC_IRQ_NUM      294
#define PCIE3_X4_SYS_IRQ_NUM      295
#define PCIE3_X4_DTMI_IRQ_NUM     300
#define PCIE3_X4_EDMA_RD0_IRQ_NUM 301
#define PCIE3_X4_EDMA_RD1_IRQ_NUM 302
#define PCIE3_X4_EDMA_WR0_IRQ_NUM 303
#define PCIE3_X4_EDMA_WR1_IRQ_NUM 304

#define PCIE3_4L_S_BASE_ADDR    0xF0000000U
#define PCIE3_2L_S_BASE_ADDR    0xF1000000U
#define PCIE3_1L0_S_BASE_ADDR   0xF2000000U
#define PCIE3_1L1_S_BASE_ADDR   0xF3000000U
#define PCIE3_1L2_S_BASE_ADDR   0xF4000000U
#define PCIE3_4L_DBI_BASE_ADDR  0xF5000000U
#define PCIE3_2L_DBI_BASE_ADDR  0xF5400000U
#define PCIE3_1L0_DBI_BASE_ADDR 0xF5800000U
#define PCIE3_1L1_DBI_BASE_ADDR 0xF5C00000U
#define PCIE3_1L2_DBI_BASE_ADDR 0xF6000000U
#define PCIE3_4L_APB_BASE_ADDR  0xFE150000U
#define PCIE3_2L_APB_BASE_ADDR  0xFE160000U
#define PCIE3_1L0_APB_BASE_ADDR 0xFE170000U
#define PCIE3_1L1_APB_BASE_ADDR 0xFE180000U
#define PCIE3_1L2_APB_BASE_ADDR 0xFE190000U
#define PCIE3_PHY_BASE_ADDR     0xFEE80000U

#define PCIE3_4L_S_ZONE_ADDR    0x900000000ULL
#define PCIE3_2L_S_ZONE_ADDR    0x940000000ULL
#define PCIE3_1L0_S_ZONE_ADDR   0x980000000ULL
#define PCIE3_1L1_S_ZONE_ADDR   0x9C0000000ULL
#define PCIE3_1L2_S_ZONE_ADDR   0xA00000000ULL
#define PCIE3_ZONE_LENGTH       0x40000000U /* 1GB */

#define PCIE3_4L_DBI_ZONE_ADDR  0xA40000000ULL
#define PCIE3_2L_DBI_ZONE_ADDR  0xA40400000ULL
#define PCIE3_1L0_DBI_ZONE_ADDR 0xA40800000ULL
#define PCIE3_1L1_DBI_ZONE_ADDR 0xA40C00000ULL
#define PCIE3_1L2_DBI_ZONE_ADDR 0xA41000000ULL
#define PCIE3_DBI_ZONE_LENGTH   0x400000U /* 4MB */

#ifdef __cplusplus
}

#endif

#endif /* RK3588_PARAMTERERS_H */